Adiabatic Logic: Future Trend and System Level Perspective (Google eBook)
Springer Science & Business Media, Oct 29, 2011 - Technology & Engineering - 184 pages
Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design.
What people are saying - Write a review
We haven't found any reviews in the usual places.
130 nm CMOS adiabatic circuit adiabatic gates Adiabatic Logic adiabatic losses adiabatic system area consumption bit RCA bit widths buffers capacitive load Carbon nanotube chiral clock CNTFET compared complex gates connected consumed CSEA cycle decreased dynamic losses ECRL and PFAL Ediss efficiency energy and area energy consumption energy dissipation energy saving factor ESOH field effect transistor fopt fraction frequency regime full adder Han-Carlson Hot Carrier Injection IEEE impact implementation increased input signal inverter latency lead leakage currents leakage losses log2 logic block maximum mode MOSFET NBTI nm node NMOS off-state on-resistance on-state operating frequency optimum frequency oscillator overhead due parameters phase pipeline depth PMOS device power-clock power-clock signal power-down RCA structure reduced shift simulation results Springer Science+Business Media static CMOS supply voltage switch synchronization signals threshold voltage transmission gate VESFET device voltage scaling Vth,p XOR gate