Memory System Design for Bus Based Multiprocessors, Issue 1088 |
Contents
Introduction | 1 |
Throughput Oriented Environment | 8 |
Performance Evaluation Methods for a ThroughputOriented | 15 |
8 other sections not shown
Common terms and phrases
64 Number ATUM traces barrier operation barrier phase Barrier-Spin Wait Phase benchmark GAUSS Block Size bytes bus access bus arbitration bus request bus traffic bus utilization bus width cache block cache coherence cache miss ratio Cache Organization Cache Size bytes cessors Chapter circuit switched bus CMVA models coherence protocol Computer Architecture cycles data structure design choices dynamic scheduling evaluate hardware implemented increase independent computing phase individual processor throughput lock table method loop invariants main memory latency main memory reply maximum multi throughput memory access memory system MIPS multiprocessor configurations multiprocessor simulator Normalized Execution number of processors parallel loop parallel program partial bus utilization problem problem size proportion queuing delay Ratio of Shared restricted combining scheduling critical section scheduling phase semaphore semaphore registers serial phase shared bus shared read miss shared writes speedup characteristics static scheduling STP bus test&test&set throughput-oriented environment tion TITAN traces total execution trace-driven simulation write back