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Adding Programming Support to the Controller
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Addr address bus address lines ADDRESS SOURCE REGISTER ADR M-INST Advanced Micro Devices bit-slice branch address branch table CC COUNTER clock condition MUX conditional branch Conditional jump connected CONT 51 control memory CONTROL SIGNALS control unit data bus decode DECREMENT devices diagram enable is active EXECUTE M-INST hardware incrementer instruction register instruction set interrupt request LDCT load control load counter logic machine level instruction main memory mapping PROM memory fetch micro microcode microcycle microinstruction microprocessor MICROPROGRAM MEMORY microroutine microword format multiplicand multiply MUX select NC PL nested subroutines next-address MUX operands operation output enable pipeline register port PROM memory PUSH RALU register/counter result RESULTOF M-INST RFCT rising edge routines RPCT scratchpad memory scratchpad registers shift shown in Figure SSI/MSI STACK ADDRESS SOURCE status status register subroutine tristate two's complement vector map