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A MIPS Processor with a Reconfigurable Coprocessor
A TimeMultiplexed FPGA
14 other sections not shown
accelerator algorithm applications architecture bandwidth benchmark buffer bytes cell chip circuit clock cycles column compiler components composite field configuration coprocessor Custom Computing Machines datapath defect tolerance device DRAM dynamic example execution fault simulation Field-Programmable firewall FPGA FPGAs for Custom functional units Garp gates implementation input interconnect interface iteration latency logic block mapping memory module multiplier netlist node operands operations optimization output parallel partial evaluation path PCI Pamette performance pixel place and route processing processor reconfigurable computing reconfigurable logic RFU instruction routing run-time reconfiguration Section shown in Figure signal SPARCstation specific speed speedup Splash square root SRAM stem stream structure synthesis systolic systolic array target template Teramac throughput tion vector Verilog VHDL virtual hardware VLSI wildcarding wires Xilinx