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0_RDONLY 0_WRONLY algorithm Altera array bits block buffer chapter char CHAR_TYPE clock cycles co_err_none co_process co_stream co.h compiler components computing configuration function connected consumer processes core create data stream debugging defined described desktop simulation devices embedded processor encryption example external FIR filter FPGA FPGA-based hardware and software hardware compilation hardware process hardware/software image filter implemented Impulse C application inner code loop input stream interfaces iteration JTAG key schedule language lNT_TYPE(32 logic MicroBlaze MicroBlaze processor module multiple Nios operations optimizer output stream parallel performance peripheral pipeline pixel Platform Studio pointer port PowerPC pragma programmable hardware programming model reconfigurable computing result return value shared memory shown in Figure signal sizeof(int32 software processes software test bench SOPC Builder source files specific stage std_ulogic synchronization tion uClinux unrolling unsigned Verilog VHDL void ware window write Xilinx