On-Chip Communication Architectures: System on Chip Interconnect (Google eBook)
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.
This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years
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CHAPTER 3 OnChip Communication Architecture Standards
CHAPTER 4 Models for Performance Exploration
CHAPTER 5 Models for Power and Thermal Estimation
CHAPTER 6 Synthesis of OnChip Communication Architectures
CHAPTER 7 Encoding Techniques for OnChip Communication Architectures
CHAPTER 8 Custom BusBased OnChip Communication Architecture Design
CHAPTER 9 OnChip Communication Architecture Refinement and Interface Synthesis
CHAPTER 10 Verification and Security Issues in OnChip Communication Architecture Design
CHAPTER 11 Physical Design Trends for Interconnects
CHAPTER 12 NetworksOnChip
CHAPTER 13 Emerging OnChip Interconnect Technologies
address bus AHB bus algorithm AMBA AHB AMBA Specification approach arbiter arbitration scheme bandwidth bits buffer burst bus architecture bus matrix bus width bus-based communication architectures capacitance channel chip circuit clock distribution network clock frequency clock signal CMOS communication protocol components Computer Computer-Aided Design configuration constraints crossbar crosstalk data bus data transfer decoder Design Automation Conference design flow dynamic encoding energy estimation FIGURE IEEE IEEE Transactions implementation input integrated Integrated Circuits interconnect interface International Conference IP core latency logic low power master memory module MPSoC multiple node number of buses on-chip communication architecture optimization packet parameters performance pipelined power consumption priority processor propagation delay proposed reduce request router shared bus shown in Fig signal simulation slave SoC designs static STBus switching synchronous synthesis SystemC techniques tion transition verification VLSI waveguides write data
Page 39 - M. Loghi, F. Angiolini, D. Bertozzi, L. Benini and R. Zafalon, "Analyzing on-chip communication in a MPSoC environment," in Proceedings of Design, Automation and Test in Europe Conference and Exhibition, 2004, pp.