On-Chip Communication Architectures: System on Chip Interconnect (Google eBook)

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Morgan Kaufmann, Jul 28, 2010 - Technology & Engineering - 544 pages
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Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years
  

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its awesome book, very simple language with full of knowledge.

Contents

CHAPTER 1 Introduction
1
CHAPTER 2 Basic Concepts of BusBased Communication Architectures
17
CHAPTER 3 OnChip Communication Architecture Standards
43
CHAPTER 4 Models for Performance Exploration
101
CHAPTER 5 Models for Power and Thermal Estimation
143
CHAPTER 6 Synthesis of OnChip Communication Architectures
185
CHAPTER 7 Encoding Techniques for OnChip Communication Architectures
253
CHAPTER 8 Custom BusBased OnChip Communication Architecture Design
301
CHAPTER 9 OnChip Communication Architecture Refinement and Interface Synthesis
341
CHAPTER 10 Verification and Security Issues in OnChip Communication Architecture Design
367
CHAPTER 11 Physical Design Trends for Interconnects
403
CHAPTER 12 NetworksOnChip
439
CHAPTER 13 Emerging OnChip Interconnect Technologies
473
Index
509
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Page 39 - M. Loghi, F. Angiolini, D. Bertozzi, L. Benini and R. Zafalon, "Analyzing on-chip communication in a MPSoC environment," in Proceedings of Design, Automation and Test in Europe Conference and Exhibition, 2004, pp.
Page 435 - Efficient 2d analysis/synthesis filter banks for directional image component representation," in Proceedings of the IEEE International Symposium on Circuits and Systems, May 1990.
Page 435 - HB Bakoglu, JT Walker, and JD Meindl, "A Symmetric Clock-Distribution Tree and Optimized High-Speed Interconnections for Reduced Clock Skew in ULSI and WSI Circuits," Proceedings of the IEEE International Conference on Computer Design, pp.

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