ProceedingsComputer Society Press of IEEE, 1991 - Computer architecture |
Contents
Wednesday April | 10 |
Thursday April | 11 |
Cache Conscious Designs | 39 |
Copyright | |
18 other sections not shown
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Common terms and phrases
address space algorithm alias analysis applications array average bandwidth basic block benchmarks bInf jInf block size blocking factor cache lines cache load cache misses coherence compiler compression Computer Architecture context switch copy cost cycles DECstation delay slots disk effect example execution fault fetch Figure floating point functional units global IEEE implementation improve increase instruction issue integer interference iteration jump kernel L1 cache Linpack loop unrolling machine mapping matrix memory references memory system MIPS miss rate multiple multiprocessor operating system optimal overhead page fault parallel pointer prediction prefetching Proc processor pseudo-registers RAID level ratio reduce register allocation request reuse RISC rPerf aPerf scalar scheduling scheme shows simulation software pipelining software prefetching SPARC speedup stripe units superscalar synchronization system call Table techniques thread tion trace vector registers virtual memory VLIW XIMD