IAPX 286 Hardware Reference Manual |
Contents
Interrupt Organization 310 | 3-10 |
310 | 3-13 |
Local Bus States 316 | 3-16 |
Copyright | |
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Common terms and phrases
286 local bus 82288 Bus Controller 82289 Bus Arbiter active address bus ADDRESS DECODE address latches address lines address mode address strobe ARDY ARDYEN bus cycle bus interface bus master bus operation Bus Unit byte CENL chip selects CLK cycles CMDLY COD/INTA configuration data bus data transceivers delay max DT/R dual-port memory dynamic RAM edge of CLK enable execution falling edge HLDA I/O devices iAPX 286 system inactive instruction Intel Interrupt Controller interrupt request interrupt-acknowledge Local Descriptor Table M/IO maximum memory and I/O memory devices memory subsystem MRDC Multibus MWTC non-maskable interrupt operand PCLK performance port prefetch privilege level processor clock processor extension protected mode read cycle READY input Real-Address mode RESET selector service routine shown in Figure SRDY status synchronous system bus system clock Task State Segment transceivers valid wait write cycle