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Specification and Implementation Models
and Critical Path Minimization
Memory Management Issues
3 other sections not shown
algorithm allocation analysis application approach array assignment basic groups behavior cache line causality circuit clock cycles co-partitioning coefficients communication components Computer conflict graph constraint logic programming data flow graph data path debugging defined Definition Design Automation Design Automation Conference DSP processors efficient embedded systems ESTEREL example FPGA frequency statistics function given hardware heuristic high-level synthesis HLS design horn clauses IEEE ILP formulation implemented input instruction interface iteration logic loop LPGS-partitions mapping memory accesses method methodology node on-chip memory operation optimization output parameters partitioning PE-net performance Petri net Petri nets pipe stage pipelining PLC-Automaton port-call problem process calculus process expressions process graph protocol reduced representation represents reverse mapping sequential shown in Figure signal simulation ſit solution source-level execution specification step techniques throughput tion transformations utilization variables VHDL VLSI