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A Novel 2D Filter Design Methodology for Heterogeneous Devices
Prototyping Architectural Support for Program Rollback Using FPGAs
Wayne Luk Imperial College
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acceleration application architecture arithmetic array binary bits block cache calculations candidate chip circuit CLBs clock cycles compiler components computing engine coprocessor core Decoder decomposition detection device dynamic efficient eFPGA embedded execution FD scheme Field-Programmable FIFO floating point floating-point FPGA FPGA-based functional units global register file hardware implementation IEEE input instruction interface intersection iteration JIT compilation kernel loop mantissa mapping match memory bandwidth method MicroBlaze MicroC/OS-II microprocessor modules multipliers netlist on-chip optimization output packet parallel parameters particle graphics Particle Pipe performance pipeline placed and routed ports processor radiosity radix reconfigurable computing reconfigurable hardware reconfigurable platform register file reuse ROCR rollback router scheduling signal SIMPPL controller simulation slices speculative speculative execution speed speedup stage systolic array Table task throughput tion TRANSIMS update vector velocity VHDL VidJn Virtex VPR's Xilinx