16th IEEE Symposium on Computer ArithmeticJean-Claude Bajard, Michael Joseph Schulte ARITH 2003 looks at improvements in algorithms and implementations for the basic arithmetic operations that are continually being developed to reduce area, delay, and energy consumption. The text also covers the increased complexity of arithmetic algorithms and implementations requiring new methods for testing and error analysis, and describes emerging technologies and applications that often require specialized number systems to facilitate efficient implementations. |
Contents
Computer Arithmetic An Algorithm Engineers Perspective | 2 |
MultiplePrecision FixedPoint Vector MultiplyAccumulator Using Shared Segmentation | 12 |
Some Optimizations of Hardware Multiplication by Constant Matrices | 20 |
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adder addition algebraic integer approximation architecture array binary Binary GCD algorithm bit serial bits bounds calculation circuit coefficients complexity Computer Arithmetic constant counters critical path cycles dataflow decimal defined delay denormal digit set division algorithm divisor double precision electron elementary functions encoding example exponent Figure finite field floating point format fractional function gates hardware high-radix IEEE Trans IEEE Transactions ILNS implementation input interval iteration latency log2 logarithm logic machine number method modular modulo multiplier normal basis number system on-line operands operations optimal output parallel partial product partial remainder performed polynomial Power4 prescaling proposed quad precision quotient digit radix radix-4 recoding reduced redundant relative error representation result rithm rounding mode scaled Section signal significand single precision square root SRT division Step subtraction systolic Table Theorem tion truncation underflow vector VLSI XOR gates zero