What people are saying - Write a review
We haven't found any reviews in the usual places.
LookAside Techniques for Minimum Circuit Memory Translators
A Design Technique for Synthesis of FaultTolerant Adders
Design of Totally SelfChecking Check Circuits for MOut ofN Codes
8 other sections not shown
adder algorithm applied arithmetic assignment assume audits b-adjacent bit group binary block Boolean functions bubble memory byte cell checker circuitry code words combinational combinational logic complete cost d-cube decoder denote elements encoded equations example failure fault simulation fault-free fault-tolerant Figure FVTS gate given half adders hardware homing sequence IEEE IEEE Trans implementation lines logic network logical values m-out-of-n code matrix memory method micro-operations microprogram module Morphic Boolean Function multiple fault node normal occur operation paper parity parity bit partition path pattern performed possible primary inputs problem procedure processor realized redundancy Reed-Muller codes reliability result self-checking self-testing sequential circuits sequential machine shown signal single faults software bugs spacecraft spare SPOOF status register step structure switch techniques test set Theorem tion tolerant transition translator unit variables