## 1972 International Symposium on Fault-Tolerant Computing: Digest of Papers : Newton, Massachusetts, June 19-21, 1972 |

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### Contents

LookAside Techniques for Minimum Circuit Memory Translators | 14 |

A Design Technique for Synthesis of FaultTolerant Adders | 20 |

Design of Totally SelfChecking Check Circuits for MOut ofN Codes | 30 |

Copyright | |

8 other sections not shown

### Common terms and phrases

adder algorithm applied arithmetic assignment assume audits b-adjacent bit group binary block Boolean functions bubble memory byte cell checker circuitry code words combinational combinational logic complete cost d-cube decoder denote elements encoded equations example failure fault simulation fault-free fault-tolerant Figure FVTS gate given half adders hardware homing sequence IEEE IEEE Trans implementation lines logic network logical values m-out-of-n code matrix memory method micro-operations microprogram module Morphic Boolean Function multiple fault node normal occur operation paper parity parity bit partition path pattern performed possible primary inputs problem procedure processor realized redundancy Reed-Muller codes reliability result self-checking self-testing sequential circuits sequential machine shown signal single faults software bugs spacecraft spare SPOOF status register step structure switch techniques test set Theorem tion tolerant transition translator unit variables