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Plenary Session O Garcia Chairman
A Very Large Data Base Computer
SIMD Architecture M Duff Chairman
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algorithms analysis applications binary bits block bubble memories buffer bytes cell cessing cessor chip circuit communication Computer Architecture Conf conveyor belt convolution cost cycle data base processor defined devices diff3 disk display encoding example execution frame function hardware host IEEE IEEE Trans Illiac IV image data image database image processing image segments implementation input instruction interconnection network interface kernel language Lisp processors logic mask matrix matrix multiplication memory modules microprocessors MIMD moblet mode multiple multiprocessor node operating system output parallel processing partition Pattern Recognition performed PICCOLO pictorial relation picture pipeline pixels problem Proc query reconfigurable resampling result Section sequential shown in Figure signal SIMD simulation speed stack STARAN storage stored string structure systolic array target tion tree tuple unit VLSI worker computer ZMOB