1985 IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management, Miami Beach, Florida, November 18-20, 1985 |
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Contents
Buffering in Macropipelines of Systolic Arrays | 2 |
A VLSI Array Processor for Image Processing Systems | 18 |
Parallel Algorithms for Image Template Matching on Hypercube SIMD Computers | 33 |
Copyright | |
34 other sections not shown
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Common terms and phrases
algorithm applications architecture array processor binary binary images bit plane block buffers cell classification column complexity component computer vision configuration connected convex hull corresponding cycle data structure defined detection edge efficient example execution feature extraction filter frame function geometric global graph hardware Hough transform hypercube IEEE IEEE Trans image data image memory image processing image understanding implementation input interconnection iteration labeling machine mapping mask matrix mesh MIMD modules multiple neighbor neighborhood node object operations optical output parallel computer parallel processing pattern recognition PE's perform pictorial database pipeline pixels polygon problem Proc procedure processing elements pyramid Radon transform reconfigurable representation result rotation scan sequence shown in Figure SIMD stage step stored symbol syntactic pattern recognition systolic array task techniques template tion tree vector VLSI
Bibliographic information
| Title | 1985 IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management, Miami Beach, Florida, November 18-20, 1985 |
| Editor | IEEE Computer Society |
| Publisher | IEEE Computer Society Press, 1985 |
| ISBN | 0818606622, 9780818606625 |
| Length | 534 pages |
| Export Citation | BiBTeX EndNote RefMan |