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Executive Perspective and Vision of the Future of
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31st ACM/IEEE Design ACM/IEEE Design Automation algorithm applied approach assignment behavior benchmark Boolean functions bound capacitance cell chip circuit clock cycles clock period clock tree CMFVS combinational complexity component Computer Computer-Aided Design connected constraints corresponding cost cube defined denoted Design Automation Conference edge Elmore delay error example experimental results fanout fault coverage feedback vertex set finite state machine flip-flops formal verification FPGA gate global routing hardware heuristic IEEE implementation interconnect interface iterations layout logic logic synthesis loop mapping matching method minimize minimum modules nets node non-robust operations optimization partitioning performance placement primary inputs primary output problem Proc procedure reduce retiming scan schedule Section segment sequential shown in Figure Signal Graph simulation solution step switch synthesis Table technique test-point testable Theorem tion transition transition relation variables vector verification vertex vertices VHDL VLSI wire