1998 11th Annual IEEE International Asic Conference: Microrfiche
Institute of Electrical and Electronics Engineers,Incorporated, 1998 - Computers - 400 pages
What people are saying - Write a review
We haven't found any reviews in the usual places.
A High Performance VLSI Cryptographic Chip
Designing A Java Microprocessor Core Using FPGA Technology
60 other sections not shown
adder algorithm analog applications architecture array ASIC ASIC design behavioral capacitance capacitor chip circuit clock cycle CMOS CMOS technology Computer control unit core counter current mirror CVTL data path devices DRAM dynamic estimation fanout fault coverage Figure filter FPGA frequency function gate hardware HD buffer IEEE implementation increase input instruction Integrated Circuits integrator interconnect interface inverter Java layout LFSR logic block loop low power memory methodology microcontroller modules MOSFET multiple netlist node noise opamp operation operational amplifier optimization paper parameters partitioning performance pipeline pixel placement power consumption power dissipation processor propagation delay reduce scheduling sensor shown in Fig simulation slew rate speed stage standard cells static structure substrate supply voltage switching synthesis Table technique testability tion tool transistor vector VHDL VLSI waveform wire load