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Josep Torrellas University of Illinois
Control Speculation in Multithreaded Processors through Dynamic Loop Detection
Performance Study of a Concurrent Multithreaded Processor
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address space ADSM Alewife algorithm allocated applications array bandwidth benchmarks bits block branch branch prediction buffer bytes cache coherence cache line cluster coherence communication compiler Computer Architecture copy cycles data dependences data transfer deadlock detection diffs disk Distributed Shared Memory evaluate execution Figure FPGA global hardware IEEE implementation instruction iteration kernel latency load lookup loop machine main memory mapped MB/s mechanism memory bus message passing misses multicast Multiplexed multiprocessors multithreading Myrinet network interface operating system optimization overhead packets page fault parallel partition path performance physical address physical register pipeline prediction prefetching processor protocol register level remote request S-COMA scheduling scheme Section shared memory Simple Coma simulation SMP nodes speculative speculative execution speedup superscalar superthreaded synchronization Table techniques thread tiling tion traffic TreadMarks treegion updates user-level virtual virtual-physical workstation wormhole write