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FIR Filters Amplifiers
Based on Envelope Detection Beex A A and Shan Peijun Virginia Tech
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adder cell algorithm amplifier applications architecture array benchmark BIBO stability BiCMOS binary block Booth encoding buffer cache capacitance charge pump chip CLBs clock CMOS coding coefficient Computer configuration constraint cycle datapath delay diagram dynamic encoding error fault coverage Figure filter finite field flip-flop FPGAs frequency full adder function gate graph hardware IEEE IEEE Trans implementation input signal Integrated Circuits interface inverter layout linear logic families low power low-power method minimal module multiplier NMOS node OCLB operation optimal output paper parameters path performance pipelined polynomial power consumption power dissipation Proc processor proposed pulse pumping circuit reduce scan sequence shown in Fig simulation results Solid-State Circuits speed stage structure supply voltage switching activity symbols synthesis Table technique test pattern threshold voltage tion transistors transition variables VHDL Viterbi decoder VLSI wavelet