ProceedingsAssociation for Computing Machinery, 1993 - Computer-aided design |
Contents
Keynote Address | 1 |
A Yu and T | 24 |
INCREASING DESIGN QUALITY AND ENGINEERING PRODUCTIVITY THROUGH | 48 |
Copyright | |
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Common terms and phrases
ACM/IEEE Design Automation algorithm analysis approach assignment behavioral benchmark binary block Boolean functional bound cell clock combinational computation Computer-Aided Design Conf constraints cost critical path data path delay model denote Design Automation Conference detected edge efficient Elmore delay example experimental results fanin fanout fault coverage Figure finite state machine flip-flops FPGA gate delay gate g graph hazards heuristic IEEE implemented independent fault sets initial iteration latches layout logic module logic synthesis maximum method MFFC minimization minimum node obtained operation optimization output parameters partial scan partitioning performance primary inputs problem Proc procedure processors reduce routing Section selected sensitizable sensitization sequence sequential circuits shown signal simulation sink solution Steiner tree synthesis system Table techniques technology mapping test pattern test set test vectors testability Theorem tion transition traversal variables verification VHDL VLSI wire worst-case Xilinx