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ATTs WE 32bit Microprocessors and Peripherals
The Inmos Transputer
Intels 80386 and 80486 Families
3 other sections not shown
32 bits 32-bit microprocessors address bus address register address space address translation addressing modes allow architecture asserted base address bit field bus controller bus cycle byte cache control cache memory chip clock co-processor contains control register controlled transfer data bus data cache data types descriptor table device displacement DSACKx dynamic bus sizing exception external fault floating point function code hardware implemented indicate Inmos input instruction cache instruction prefetch instruction set integer interrupt stack linear address logical address long word main memory memory management Memory Management Unit Occam offset operand operating system output page table performance peripheral physical address pipelined port prefetch privilege level program counter provides read cycle reset Section segment descriptor segment register selector shown in Fig signal specified Stack Pointer status register string supervisor synchronous translation tables transputer virtual address write cycle