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Chapter 6 Math Coprocessor Interface This describes the 386 SL CPU math
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active low address bus address space banks battery BIOS buffer bus cycle byte cache controller cache SRAMs chip select Configuration register control signals CPU clock CPU reset data bus deasserted decoded devices disabled DRAM drive enabled EPROM external bus master external RTC falling edge Figure flash disk floppy disk controller hard disk hard disk interface I/O address I/O read interrupt request IOCHRDY ISACLK2 Kbytes keyboard controller latched main memory mapping math coprocessor Mbytes memory access memory controller memory read memory write memory-mapped I/O Microprocessor Programmer's Reference non-cacheable operation options parallel port peripherals Pi-bus pins power consumption power management programmed Programmer's Reference Manual PSTART read cycle refresh cycle serial port SL CPU SL CPU output SL input SL Microprocessor Programmer's SL output SL SuperSet SL SuperSet system SRAM standby SYSCLK system address system management interrupt timer wait-state write access write cycles