## 5th International Conference on High Performance Computing, Volume 5 |

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### Contents

New Number Representation and Conversion Techniques on Reconfigurable Mesh | 2 |

Precise Control of Instruction Caches | 11 |

More on Arbitrary Boundary Packed Arithmetic | 19 |

Copyright | |

30 other sections not shown

### Common terms and phrases

allocation analysis applications architecture array bandwidth binary bits block block size branch prediction broadcast buffer CC-NUMA cluster communication complexity Computer cost cycles data cache database delay disk distance transform distributed dynamic edge efficient elements Euclidean distance execution fetched Figure flits function given global graph HighSP hypercube IEEE implementation inode input instruction integer iteration latency Lemma lightpath load balancing lock loop machine mapping memory method multiple node number of processors objects operations optimal output overhead packet paper parallel algorithm parallel computing path performance pixel prediction prefetch prefetch buffer Prefix Sums problem Proc processor proposed protocol query queue reconfigurable mesh reference representation rithm routing S-COMA schedule scheme Section sequential simulation skeleton SPMD step Supernode superscalar switch techniques Theorem tion topology traffic tree University unrolling virtual channel wavelength workload