ARM Architecture Reference Manual
Addison-Wesley, 2001 - Computers - 816 pages
About the ARM Architecture The ARM architecture is the industry's leading 16/32-bit embedded RISC processor solution. ARM Powered microprocessors are being routinely designed into a wider range of products than any other 32-bit processor. This wide applicability is made possible by the ARM architecture, resulting in optimal system solutions at the crossroads of high performance, low power consumption and low cost. About the book This is the authoritative reference guide to the ARM RISC architecture. Produced by the architects that are actively working on the ARM specification, the book contains detailed information about all versions of the ARM and Thumb instruction sets, the memory management and cache functions, as well as optimized code examples.
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Chepter A3 The ARM lnstruction
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The condition fietd A35
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1always1 condition 1MPLEMENTATroN DEF1NED 1see access permissions addressing mode addressing_mode ahove alignmeat ARM architecture ARM instruction ARM processor cache line coatains coatrol comains condition field conditions are defined coprocessor coprocessor instructions CP15 register CPSR Data Ahort datn-processing descrihed descriptor destination register disahled enahled encoding endianness Exceptions None Operation executed The conditions floating-poim FPSCR general-purpose registers handler hase address hetween hlock hoth hottom hranch hyte iateger iaterrupt imeger imerrupt implemeatation implememation instruction cache instruction is executed instruction set invalidate lf cond lnstruction Load and Store lockdown ls the condition main memory memory access memory coherency memory system normal offset opcode opcode2 operand perform possihle Prefetch protection regions result Rn Rd second-level shifter_operand single-precision source register Specifies the register SPSR Status Register suhtraction Syntax Thumh instruction translation tahle umltiply umst UNPRED1CTABLE updated User mode variaats variams vector virtual address write huffer Yes Yes Yes zero