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Synthesis for Testability of PLA Based Finite State Machines
A Concurrent Fault Detection Method for Superscalar Processors
A Method of Diagnosing Logical Faults in Combinational Circuits
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3-state algorithm ALSC analog analog circuits applied approach array ATPG benchmark circuits boundary scan clock CMOS combinational circuit Computer Computer-Aided Design Conf configuration considered corresponding crosstalk cycle data path delay denotes example Experimental results fanout fault coverage fault detection fault diagnosis fault list fault model fault simulation fault-free flip-flops FPGA function gate graph IEEE IEEE Trans implemented initial input pattern input sequence Inverting LFSR linked faults logic value machine mapping memory cell method module node number of test observed obtained overhead partitioning primary input primary output Proc propagation proposed random redundant retiming scan chain scan design scheme Section sequential circuits shift shown in Figure signal structure stuck-at faults subcircuit Table target fault technique test application test length test patterns test sequence test set test vectors testability tion transformation transition VLSI voltage XOR gates