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ALGORITHM LEVEL WORKLOAD CHARACTERIZATION
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ACS operation active mode baseband processing block buffer CDMA channel decoder channel estimator column components computation kernels computation pattern convolutional code correlation cycle data alignment data load data load/store data memory data movement pattern demodulator descrambler despreader dynamic power encoder energy cost FFT operation FIR filter following equation hardware high level architecture idle mode IEEE implemented input data input operands interleaver macro instructions macro operations major kernels min/max finding minimize multipath searcher multiple nodes OFDMA operation frequency operation mode packet data service parallel datapath parallelizable kernels performs physical layer power consumption power efficiency processor proposed architecture register file scalar datapath sequence shown in Figure SIMD staggered execution system throughput TDMA throughput and power trellis diagram Turbo codes Turbo decoder vector alignment vector computation vector reduction vector registers Viterbi decoder Viterbi-BMC/ACS W-CDMA W-CDMA physical layer wireless channel wireless communication wireless terminals WWAN