A Framework for Automated HW/SW Co-Verification of SystemC Designs Using Timed Automata

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Logos Verlag Berlin GmbH, 2010 - Computers - 145 pages
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In this dissertation, we present a systematic, comprehensive, and formally founded quality assurance process, which allows automated co-verification of digital hardware/software systems that are modeled in SystemC. The main idea is to apply model checking to verify that an abstract design meets a requirements specification and to generate conformance tests to check whether refined designs conform to this abstract design. As formal foundation, we define a formal semantics of SystemC by a transformation into the well-defined semantics of UPPAAL timed automata. The automatically generated timed automata model can be verified using the UPPAAL model checker and it can be used to generate conformance tests. With that, we obtain guarantees about liveness, safety, and timing properties of the abstract design, which serves as a specification, and we can ensure the consistency of each refined design to that. The result is a HW/SW co-verification flow that supports the HW/SW co-development process continuously from abstract design down to the implementation. The complete verification flow is implemented in our Framework for the Verification of SystemC designs using Timed Automata (VeriSTA) and its applicability and performance are shown by experimental results.
 

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Contents

Introduction
13
Background
21
Related Work
57
Quality Assurance Approach
63
FormalSemantics for SystemC
69
Conformance Testing
85
Implementation
107
Experimental Results
115
Conclusion
127
List of Figures
133
Bibliography
139
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