A Practical Introduction to Computer Architecture

Front Cover
Springer Science & Business Media, Apr 21, 2009 - Computers - 642 pages
It is a great pleasure to write a preface to this book. In my view, the content is unique in that it blends traditional teaching approaches with the use of mathematics and a mainstream Hardware Design Language (HDL) as formalisms to describe key concepts. The book keeps the “machine” separate from the “application” by strictly following a bottom-up approach: it starts with transistors and logic gates and only introduces assembly language programs once their execution by a processor is clearly de ned. Using a HDL, Verilog in this case, rather than static circuit diagrams is a big deviation from traditional books on computer architecture. Static circuit diagrams cannot be explored in a hands-on way like the corresponding Verilog model can. In order to understand why I consider this shift so important, one must consider how computer architecture, a subject that has been studied for more than 50 years, has evolved. In the pioneering days computers were constructed by hand. An entire computer could (just about) be described by drawing a circuit diagram. Initially, such d- grams consisted mostly of analogue components before later moving toward d- ital logic gates. The advent of digital electronics led to more complex cells, such as half-adders, ip- ops, and decoders being recognised as useful building blocks.
 

What people are saying - Write a review

We haven't found any reviews in the usual places.

Contents

Mathematical Preliminaries
3
111 Connectives
5
112 Quantifiers
7
113 Manipulation
8
12 Sets and Functions
10
121 Construction
11
122 Operations
12
123 Numeric Sets
14
822 Nonvolatile RAM and ROM
293
823 Magnetic Disks
294
824 Optical Disks
296
825 Error Correction
297
83 Basic Cache Memories
300
831 Fetch Policy
303
832 Write Policy
304
833 DirectMapped Caches
305

125 Relations
17
13 Boolean Algebra
18
131 Boolean Functions
21
132 Normal Forms
22
14 Number Systems
23
141 Converting Between Bases
25
142 Bits Bytes and Words
27
143 Representing Numbers and Characters
29
15 Toward a Digital Logic
40
16 Further Reading
41
17 Example Questions
42
Basics of Digital Logic
43
212 Building and Packaging Transistors
44
22 Combinatorial Logic
48
222 3state Logic
50
223 Designing Circuits
51
224 Simplifying Circuits
53
225 Physical Circuit Properties
61
226 Basic Building Blocks
63
23 Clocked and Stateful Logic
74
231 Clocks
75
232 Latches
77
233 FlipFlops
80
234 State Machines
81
24 Implementation and Fabrication Technologies
87
242 Programmable Logic Arrays
90
243 Field Programmable Gate Arrays
92
25 Further Reading
93
Hardware Design Using Verilog
97
312 Design Automation as a Solution
98
32 Structural Design
100
322 Wires
101
323 Values and Constants
103
324 Comments
104
325 Basic Instantiation
105
326 Nested Instantiation
108
33 Higherlevel Constructs
109
331 Continuous Assignments
110
332 Selection and Concatenation
112
333 Reduction
114
34 State and Clocked Design
115
342 Processes and Triggers
117
343 Procedural Assignments
118
344 Timing and Delays
120
345 Further Behavioural Statements
121
346 Tasks and Functions
126
35 Effective Development
127
351 System Tasks
128
352 Using the Preprocessor
129
353 Parameters
131
354 Named Port Lists
132
355 Generate Statements
133
356 Simulation and Stimuli
134
36 Further Reading
136
37 Example Questions
137
Processor Design
142
A Historical and Functional Perspective
143
42 SpecialPurpose Computers
144
43 GeneralPurpose Computers
146
44 Stored Program Computers
150
45 Toward Modern Computers
158
451 The von Neumann Bottleneck
160
453 SelfModifying Programs
161
46 Further Reading
166
Basic Processor Design
169
511 Major Datapath Components
171
512 Describing Instruction Behaviour
174
513 The FetchDecodeExecute Cycle
176
52 Buses
177
522 Asynchronous Buses
178
53 Addressing Modes
179
531 Immediate Addressing
180
54 Instruction Encoding
183
542 Instruction Formats
186
544 More Complicated Encoding Issues
189
55 ControlFlow
192
551 Predicated Execution
194
552 Function Calls
197
56 Some Design Philosophy
198
562 RISC versus CISC
199
57 Putting It All Together
200
58 Further Reading
208
59 Example Questions
209
Measuring Performance
213
611 Estimating Execution Time
214
612 Measuring Execution Time
216
613 Benchmark Programs
218
614 Measuring Improvement
219
62 Further Reading
220
Arithmetic and Logic
223
72 Comparisons
224
721 Unsigned Comparisons
225
722 Signed Comparisons
228
732 Subtraction
233
74 Shift and Rotate
236
741 BitSerial Shifter
238
742 Logarithmic Shifter
241
75 Multiplication
243
751 BitSerial Multiplier
245
752 Tree Multiplier
249
753 DigitSerial Multiplier
250
754 Early Termination
251
755 Wallace and Dadda Trees
253
756 Booth Recoding
257
76 Putting It All Together
259
762 Arithmetic ALU
262
77 Further Reading
265
78 Example Questions
266
Memory and Storage
269
811 Historical Memory and Storage
271
812 A Modern Memory Hierarchy
277
813 Basic Organisation and Implementation
279
814 Memory Banking
288
815 Access Locality
290
82 Memory and Storage Specifics
291
834 FullyAssociative Caches
310
835 SetAssociative Caches
312
836 Cache Organisation
315
84 Advanced Cache Memories
316
842 Gated and Drowsy Caches
319
85 Putting It All Together
321
851 Register File
322
852 Main Memory
323
853 Cache Memory
324
86 Further Reading
329
Advanced Processor Design
331
911 A Taxonomy of Parallelism
332
912 InstructionLevel Parallelism ILP
335
92 Pipelined Processors
339
921 Pipelined Circuits
343
922 Pipelined Processors
347
923 Pipeline Hazards
350
924 Stalls and Hazard Resolution
352
93 Superscalar Processors
360
Scoreboardbased Design
361
Reservation Stationbased Design
370
934 Further Improvements
378
94 Vector Processors
380
942 A Dedicated Vector Processor
382
943 SIMD Within A Register SWAR
384
944 Issues of Vectorisation
386
95 VLIW Processors
389
96 Further Reading
390
Part III The HardwareSoftware Interface
394
Linkers and Assemblers
397
102 The Memory Model
400
1021 Stack Section
401
1022 Static Data Section
402
1023 Dynamic Data Section
403
103 Executable Versus Object Files
407
104 Linkers
410
1041 Static and Dynamic Linkage
413
1042 Bootstrap Functions
415
1043 Symbol Relocation
416
1044 Symbol Resolution
417
1051 Basic Assembly Language Statements
418
1052 Using Machine Instructions
420
1053 Using Assembler Aliases
429
1054 Using Assembler Directives
431
1055 Peephole Optimisation
434
1056 Some Short Example Programs
435
1057 The Forward Referencing Problem
439
1058 An Example Assembler
441
106 Further Reading
449
Compilers
451
112 Compiler Bootstrapping and ReHosting
453
113 Intermediate Representation
454
114 Register Allocation
457
1141 An Example Allocation
461
1142 Uses for Precolouring
463
1143 Avoiding Error Cases via Spilling
464
115 Instruction Selection and Scheduling
467
1151 Instruction Selection
468
1152 Instruction Scheduling
470
1154 Scheduling Instructions
471
116 Template Code Generation for HighLevel Statements
473
1161 Conditional Statements
475
1162 Loop Statements
477
1163 Multiway Branch Statements
478
117 Template Code Generation for HighLevel Function Calls
479
1171 Basic Stack Frames
481
1172 Advanced Stack Frames
485
118 Further Reading
491
119 Example Questions
492
Operating Systems
495
122 The HardwareSoftware Interface
497
1222 MIPS32 Processor Modes
499
1223 MIPS32 Assembly Language
500
123 BootStrapping
501
124 Event Management
502
1241 Handling Interrupts
503
1242 Handling Exceptions
505
1243 Handling Traps
506
1244 An Example Exception Handler
510
125 Memory Management
511
1251 Basic Concept
512
1252 Pages and Frames
515
1253 Address Translation and Memory Access
518
1254 Page Eviction and Replacement
520
1255 Translation Lookaside Buffer TLB
521
126 Process Management
522
1261 Storing and Switching Process Context
523
1262 Process Scheduling
524
1263 An Example Scheduler
529
127 Further Reading
533
128 Example Questions
534
Efficient Programming
535
132 Space Conscious Programming
536
1322 Reducing Memory Allocation
537
133 Time Conscious Programming
540
1332 Branch Elimination
541
1333 Loop Fusion and Fission
542
1334 Loop Unrolling
545
1335 Loop Hoisting
546
1336 Loop Interchange
548
1337 Loop Blocking
549
1338 Function Inlining
551
1339 Software Pipelining
554
134 Example Questions
556
Appendices
560
SPIM A MIPS32 Simulator
561
A2 Configuring SPIM
562
A3 Controlling SPIM
563
A4 Example Program Execution
565
A5 Using System Calls
570
Example Solutions
573
References
629
Index
633
Copyright

Other editions - View all

Common terms and phrases

Bibliographic information