A Primer on Memory Consistency and Cache Coherence
Morgan & Claypool Publishers, 2011 - Computers - 197 pages
Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies
What people are saying - Write a review
We haven't found any reviews in the usual places.
Other editions - View all
Atomic Transactions broadcast C1 Core C2 cache block cache coherence cache controller changes the block chapter chip coherence controller coherence protocol coherence requests coherence transactions Computer Architecture Core C1 Core C1 Core core’s data to Req data1 data2 deadlock denotes directory controller directory protocols evict example FENCE Figure Fwd-GetS GetM hit stall stall HyperTransport IBM Power interconnection network Inv-Ack Invalidation issue L1 caches livelock LLC/memory loads and stores LWSYNC memory consistency model memory controller memory location memory model memory order memory system MESI MSI protocol multicore Multiprocessor node operations optimizations owner performance Power5 prefetch primer Proceedings ofthe program order Put-Ack to Req PutM read-only read-write relaxed models remove Req reorder SC executions send data sequential consistency shared memory snooping protocols specification speculative execution stall stall send stall stall stall system model TABLE total order transient transition update write buffer