A designer's guide to VHDL synthesis
A Designer's Guide to VHDL Synthesis is intended for both design engineers who want to use VHDL-based logic synthesis ASICs and for managers who need to gain a practical understanding of the issues involved in using this technology. The emphasis is placed more on practical applications of VHDL and synthesis based on actual experiences, rather than on a more theoretical approach to the language. VHDL and logic synthesis tools provide very powerful capabilities for ASIC design, but are also very complex and represent a radical departure from traditional design methods. This situation has made it difficult to get started in using this technology for both designers and management, since a major learning effort and 'culture' change is required. A Designer's Guide to VHDL Synthesis has been written to help design engineers and other professionals successfully make the transition to a design methodology based on VHDL and log synthesis instead of the more traditional schematic based approach. While there are a number of texts on the VHDL language and its use in simulation, little has been written from a designer's viewpoint on how to use VHDL and logic synthesis to design real ASIC systems. The material in this book is based on experience gained in successfully using these techniques for ASIC design and relies heavily on realistic examples to demonstrate the principles involved.
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Making the Transition to VHDL Synthesis
Typical ASIC Development Flow
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15 downto adder ADDR applications Architecture RTL array ASIC design basic Begin If Reset binary counter block diagram Chapter clock edge clocked process combinational logic Constant Databus dataflow decode defined delay design process design tools edge detector Elsif Rising_Edge Clock enable End Process End RTL Entity enumerated type FIFO flip flops gate count gate level Gray code Graycnt implement IN_BUS input Integer Integer Range Leading Edge Detector load logic design logic functions logic simulation logic synthesis loop machine multiplexer multiplier netlist Next_State operation optimization output Pgen problem Process Clock PULSEGEN Reg_A Reg_B result retriggering schematic sequencer sequential logic shown in Figure Signal Assignment signal names simple specific speed stack statement Std_Ulogic Std_Ulogic_Vector 7 downto synchronous syntax technique test bench test patterns testability TRIG Trigger two's complement Type Conversion Upcount variable VHDL code VHDL description VHDL language VHDL simulation VHDL synthesis waveforms ZERO