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Architecture and Programming Model
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Address Space Architecture Address Space implementation algorithm applications artifactual communication atom back-end boxes cache blocks cache coherence protocol cache misses chapter coherence events computation partitioning Computer Architecture consistency model cycle data decomposition data distribution data localized data partition data set demonstrated described dissertation distributed address space distributed shared memory Dual Address Space efficient enable ensure execute false sharing Fast Multipole Method Figure front-end global address space global memory granularity hardware hardware-based HYCOM interaction phases interface invalidate Itanium iteration L3 misses load localized data locks loop mechanism memory instructions memory operations memory system message passing modified molecular dynamics MPI version MSI protocol node non-local data number of processors ocean octtree OpenMP parallel performance physical registers potential problem reduction operator redundant computation release consistency scalability semaphore sequential consistency SGI Altix shared address space sharing list significantly standard protocol synchronization operations time-step transaction tree-code User-Controllable Coherence variant