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DOMINANCE PARTITIONS AND INTERVALS
AND IRREDUCIBLE GRAPHS
VERTEX ORDERING ALGORITHMS
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Algorithm analysis arcs assembly language assume available on entrance available on exit back dominator back-latches basic block busy on entrance busy on exit characteristic vector circuit compile-time computations compiler variable computed downward connectivity matrix control flow graph cycle of G defined definition derived graph directed graph distributive lattice eliminate entry node equivalence Example execution frequency exists EXIT EXIT EXIT expressions Figure FORTRAN global optimization graph G graph of Fig Hence inductive variable instruction INTERVAL EXIT interval head irreducible graph iteration killed loop constant Loop Optimization minimal modified node optimizing compiler partition paths of length point of confluence prime cycles program graph program loops programming languages Proof PROPOSITION recompilation reducible reduction in strength redundancy equations register allocation sequence shown in Fig simple path split graph strongly connected subgraph Subroutine Linkages summand Theorem tion transformations v-busy path vertex vertices