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Speech Processing Considerations
A Parallel Pipeline Multicomputer Architecture
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4-bit slice A/D module ABC's addition algorithms Array-Block Computer array-block pipeline autocorrelation bit slices block diagram buffer Cepstrum Cepstrum Method chip complex computer block configuration connectors control lines Control Memory control store cost data frame data memory data transfer delay digital signal processing digital speech processing display domain example extractor fast Figure filter floating point formant frame of data frequency given frame hardware IC's input intercomputer communication interconnecting large number linear prediction Linear Prediction Coefficient load machine memory location microinstruction microprocessors microprogram microwords minicomputer multiplexed multiplication multiprocessor operation output P2 architecture P2 bus P2 system package Parallel Pipeline performance pitch extraction pitch period processing tasks PROM's pulse real time speech reconfiguration reliability sampling serial shown in Fig software bus spectrum speech processing speech recognition speed synchronous tion transfer clock two's complement uniprocessor vocal tract word zero