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The HSP Architecture
A Comparison of Representation in HSII and HSP
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action execution address space adequacy array artificial intelligence Blackboard C.mmp Chapter comparison condition elements condition evaluation context cost Cycle 15 Cycle 9 data-directed invocation declarative knowledge declarative long-term deletes directionality encoded factor Fennell and Lesser field Figure global working memory HSII and HSP HSII KSs HSII system HSP architecture HSP kernel HSP POM HSP productions HSP's HSP/HSII Hydra implementation input integer Kbits knowledge units large number locking long-term knowledge match msec multiple multiprocessor Newell number of processors number of productions operating optimization orders of magnitude overhead overlay PM index POM run POM VPRB possible primary memory primitives procedural procedural knowledge PSNLST queue ratio recognition representation RPOL Rychener SASS segment simulator small address problem speech knowledge speech understanding syllable syllable nucleus synchronization tion translated to HSP utilization Cycle utterance variable vowel probabilities WM changes WM elements WM searching