Advanced computer arithmetic design
Innovative techniques and cutting-edge research in computer arithmetic design
Computer arithmetic is a fundamental discipline that drives many modern digital technologies. High-performance VLSI implementations of 3-D graphics, encryption, streaming digital audio and video, and signal processing all require fast and efficient computer arithmetic algorithms. The demand for these fast implementations has led to a wealth of new research in innovative techniques and designs.
Advanced Computer Arithmetic Design is the result of ten years of effort at Stanford University under the Sub-Nanosecond Arithmetic Processor (SNAP) project, which author Michael Flynn directs. Written with computer designers and researchers in mind, this volume focuses on design, rather than on other aspects of computer arithmetic such as number systems, representation, or precision.
Each chapter begins with a review of conventional design approaches, analyzes the possibilities for improvement, and presents new research that advances the state of the art. The authors present new data in these vital areas:
* Addition and the Ling adder
* Improvements to floating-point addition
* Encoding to reduce execution times for multiplication
* The effects of technology scaling on multiplication
* Techniques for floating-point division
* Approximation techniques for high-level functions such as square root, logarithms, and trigonometric functions
* Assessing cost performance of arithmetic units
* Clocking to increase computer operation frequency
* New implementation of continued fractions to the approximation of functions
This volume presents the results of a decade's research in innovative and progressive design techniques. Covering all the most important research topics in the field, Advanced Computer Arithmetic Design is the most up-to-date and comprehensive treatment of new research currently available.
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Multiplication with Partially Redundant Multiples
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ABC Carry Sum adder addition algorithm approximation approximation error average back-solved binary numbers binary tree bit slice Boolean elements capacitance Carry Sum ABC carry-save circuit clock CMOS column compressor compute correct bits Counter Carry Sum critical path cycle direct multiplier division divisor encoding schemes excess CPI function FUPA gate delays hardware implementation increases input interconnect latency logic lookup table M-log fraction maximum number minimum Mu1tip1icand non-Booth number of bits number of correct number of counter number of digits number of tracks operand optimization partial products partial remainder performance polynomial processor propagation delay proposed method quotient digits radix reciprocal operation reduced redundant Booth result rows shift shown in Figure significand square root step Taylor series tion topologies tracks per channel transistors truncation vector VLSI voltage Wallace tree wave pipelining wires XX XX XX