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General Structure of Microprocessors
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32 bits 4-kbyte addr addressing modes Alpha arithmetic byte Chap chip CISC condition codes control register Coprocessor Courtesy of Intel Courtesy of Motorola cycle data bus data cache data registers decode descriptor destination displacement Doubleword execution fetch flag floating-point instructions hardware illustrated in Fig immediate data implemented instruction cache instruction formats instruction pipeline instruction set integer Intel Corp interface interrupt Jump kbytes logical longword main memory Mbytes memory location microprocessors MIPS Motorola multiply offset on-chip cache opcode operand operation PA-RISC page table Pentium physical address pipeline pOEP-only pointer PowerPC prefetch processor quadword register file register indirect RISC systems RISC-type secondary cache shift shown in Fig SPARC specified stack status register Subtract superscalar SuperSPARC Table target address tion trap unit Unsigned vector virtual address word x86 architecture zero