Advanced Microprocessors |
Contents
Introduction | 3 |
Appendix to Part 1 The ASCII Character | 6 |
General Structure of Microprocessors | 9 |
Copyright | |
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32 bits 4-kbyte addr addressing modes Alpha arithmetic branch instruction byte Chap chip CISC condition codes control register Coprocessor Courtesy of Intel Courtesy of Motorola CPU register cycle data bus data cache decode descriptor destination Doubleword execution fetch floating-point instructions halfword hardware IEEE illustrated in Fig implemented instruction cache instruction formats instruction pipeline instruction set integer interface interrupt kbytes load and store Logical longword main memory Mbytes microprocessors MIPS Mnemonic Motorola multiply offset opcode operand operation PA-RISC page table Pentium physical address pipeline POEP POEP-only pointer PowerPC PowerPC 601 prefetch processor quadword queue reg2 register file register indirect RISC-type secondary cache segment shift shown in Fig SOEP SPARC specified stack status register store instructions Subtract superscalar SuperSPARC TABLE tion transfer trap unit Unsigned virtual address word x86 architecture zero