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A Comparison of 32Bit Buses
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arbitration architecture asserted backplane backplane bus bandwidth big-endian block size block transfer broadcast bus interface bus request buses cache coherence cache line circuit circuit switched clock Computer connector cycle data transfer deadline-monotonic scheduling defined delay device driver endian example execution Fastbus FDDI FIFO Figure flow control function Futurebus Futurebus+ handshake hardware IEEE Micro IEEE Standard implementation input interconnect interrupt invalidation little-endian logic main memory latency master mechanism memory system message passing metastable module multi Multibus multiple multiprocessor multiprocessor systems node Nubus open-collector operation output parallel performance phase pointer priority problem protocol rate-monotonic scheduling receiver response ring buffer Scalable scheduling segment set associativity shared bus signal simulation slave specification switched synchronous task throughput tion traffic transaction transceivers transmission transmit queue VMEbus write