Advances in Computer Systems Architecture: 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings

Pirmais vāks
Thambipillai Srikanthan, Jingling Xue, Chip-Hong Chang
Springer, 2005. gada 19. okt. - 834 lappuses
On behalf of the ProgramCommittee, we are pleased to present the proceedings of the 2005 Asia-Paci?c Computer Systems Architecture Conference (ACSAC 2005) held in the beautiful and dynamic country of Singapore. This conference was the tenth in its series, one of the leading forums for sharing the emerging research ?ndings in this ?eld. In consultation with the ACSAC Steering Committee, we selected a - member Program Committee. This Program Committee represented a broad spectrum of research expertise to ensure a good balance of research areas, - stitutions and experience while maintaining the high quality of this conference series. This year’s committee was of the same size as last year but had 19 new faces. We received a total of 173 submissions which is 14% more than last year. Each paper was assigned to at least three and in some cases four ProgramC- mittee members for review. Wherever necessary, the committee members called upon the expertise of their colleagues to ensure the highest possible quality in the reviewing process. As a result, we received 415 reviews from the Program Committee members and their 105 co-reviewers whose names are acknowledged inthe proceedings.Theconferencecommitteeadopteda systematicblind review process to provide a fair assessment of all submissions. In the end, we accepted 65 papers on a broad range of topics giving an acceptance rate of 37.5%. We are grateful to all the Program Committee members and the co-reviewers for their e?orts in completing the reviews within a tight schedule.
 

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Saturs

Keynote Address I
1
Compiler and OS for Emerging
2
EnergyEffective Instruction Fetch Unit for Wide Issue Processors
15
RuleBased PowerBalanced VLIW Instruction Scheduling with
28
An Innovative Instruction Cache for Embedded Processors
41
Dynamic Voltage Scaling for Power Aware Fast Fourier Transform
52
Methodologies and Architectures
65
A Pipelined Hardware Architecture for Motion Estimation
79
FPGAs for Improved Energy Efficiency in Processor Based Systems
440
Morphable Structures for Reconfigurable Instruction Set Processors
450
Interconnect Networks and Network
464
A New Interconnection Network Based on Matrix
478
The Channel Assignment Algorithm on RPk Networks
488
Extending Address Space of IP Networks with Hierarchical
499
Building a Terabit Router with XD Networks
520
A Direct3DBased LargeScale Display Parallel Rendering
540

Embedded Intelligent Imaging OnBoard Small Satellites
90
Architectural Enhancements for Color Image and Video Processing
104
A Portable Doppler Device Based on a DSP with High Performance
118
Processor Architectures
131
The Challenges of Massive OnChip Concurrency
157
Design of FineGrain Multicontext Reconfigurable Processing
171
Modularized Redundant Parallel Virtual File System
186
ResourceDriven Optimizations for TransientFault Detecting
200
A FaultTolerant Routing Strategy for FibonacciClass Cubes
215
Embedding of Cycles in the Faulty Hypercube
229
Improving the Performance of GCC by Exploiting IA64 Architectural
236
An Integrated Partitioning and Scheduling Based Branch
252
A Register Allocation Framework for Banked Register Files with Access
269
Irregular Redistribution Scheduling by Partitioning Messages
295
Data Value Predictions
310
Speculative Issue Logic
323
Using Decision Trees to Improve ProgramBased and ProfileBased
336
Arithmetic Data Value Speculation
353
Exploiting ThreadLevel Speculative Parallelism with Software Value
367
Keynote Address II
389
A Switch Wrapper Design for SNA OnChipNetwork
405
A Configuration System Architecture Supporting BitStream
415
Biological Sequence Analysis with Hidden Markov Models on
429
A Technique to Reduce Preemption Overhead in RealTime
566
HardwareSoftware Partitioning
580
Increasing Embedding Probabilities of RPRPs in RIN Based BIST
600
A Practical Test Scheduling Using NetworkBased TAM in Network
614
Architectures for Secured Computing
625
Efficient Architectural Support for Secure BusBased Shared Memory
640
Covert Channel Analysis of the PasswordCapability System
655
Simulation and Performance Evaluation
669
Application of RealTime ObjectOriented Modeling Technique
680
VLSI Performance Evaluation and Analysis of Systolic and Semisystolic
693
Architectures for Emerging Technologies
707
FPGA Implementation and Analyses of Cluster Maintenance
714
A Study on the Performance Evaluation of Forward Link in CDMA
728
Memory Systems Hierarchy
736
A Memory Bandwidth Effective Cache Store Miss Policy
750
ApplicationSpecific HardwareDriven Prefetching to Improve Data
761
Targeted Data Prefetching
775
Architectures for Emerging Technologies
787
Efficient VLSI Architectures for Convolution and Lifting Based
795
A Novel Reversible TSG Gate and Its Application for Designing
805
Implementation and Analysis of TCPIP Offload Engine and RDMA
818
Author Index
831
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