Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings
On behalf of all of the people involved in the program selection, the program committee members as well as numerous other reviewers, we are both relieved and pleased to present you with the proceedings of the 2006 Asia-Pacific Computer Systems Architecture Conference (ACSAC 2006), which is being hosted in Shanghai on September 6–8, 2006. This is the 11th in a series of conferences, which started life in Australia, as the computer architecture component of the Australian Computer Science Week. In 1999 it ventured away from its roots for the first time, and the fourth Australasian Computer Architecture Conference was held in the beautiful city of Sails (Auckland, New Zealand). Perhaps it was because of a lack of any other computer architecture conference in Asia or just the attraction of traveling to the Southern Hemisphere but the conference became increasingly international during the subsequent three years and also changed its name to include Computer Systems Architecture, reflecting more the scope of the conference, which embraces both architectural and systems issues. In 2003, the conference again ventured offshore to reflect its constituency and since then has been held in Japan in the beautiful city of Aizu-Wakamatsu, followed by Beijing and Singapore. This year it again returns to China and next year will move to Korea for the first time, where it will be organized by the Korea University.
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ACSAC algorithm allocation analysis applications approach architecture array bandwidth benchmarks Berlin Heidelberg 2006 binary bits block branch prediction bypass cache line cache miss chip CIALU circuit clock compiler Computer conﬁguration context switches cycle data cache diﬀerent distribution drowsy dynamic page policy dynamic voltage scaling eﬀective Egan Eds embedded energy error evaluate execution ﬁle filter ﬁrst FPGA function graph gzip Hamiltonian paths hardware hypercube IEEE implementation input instruction interface Jesshope kernel L2 cache latency leakage loop memory access microkernel mode multiple multiprocessor node operating system optimization output packets paper parallel parameters path performance Petersen Graph pipeline predictor prefetch proposed reconﬁgurable reduce register allocation runtime scheduling Section Self−Similar sensor networks server shows simulation soft error speedup stream task techniques Technology thread throughput traﬃc tuple tuple space variable voltage scaling points Xilinx