Advances in Computer Systems Architecture: 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings
Pen-Chung Yew, Jingling Xue
Springer Science & Business Media, Sep 14, 2004 - Computers - 598 pages
On behalf of the program committee, we were pleased to present this year’s program for ACSAC: Asia-Paci?c Computer Systems Architecture Conference. Now in its ninth year, ACSAC continues to provide an excellent forum for researchers, educators and practitioners to come to the Asia-Paci?c region to exchange ideas on the latest developments in computer systems architecture. This year, the paper submission and review processes were semiautomated using the free version of CyberChair. We received 152 submissions, the largest number ever.Eachpaperwasassignedatleastthree,mostlyfour,andinafewcaseseven ?ve committee members for review. All of the papers were reviewed in a t- monthperiod,duringwhichtheprogramchairsregularlymonitoredtheprogress of the review process. When reviewers claimed inadequate expertise, additional reviewers were solicited. In the end, we received a total of 594 reviews (3.9 per paper) from committee members as well as 248 coreviewers whose names are acknowledged in the proceedings. We would like to thank all of them for their time and e?ort in providing us with such timely and high-quality reviews, some of them on extremely short notice.
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adder algorithm applications area cost array bandwidth benchmarks block branch instruction branch predictor branch target buffer buffer bytes bzip2 cache line cache miss cells Cilk compiler configuration control flow cycle data cache decoder DRAM driver dynamic efficient execution fetch Figure floating point FPGA FSRAM functional units hardware hierarchy hypercube IEEE implementation input Itanium iteration kernel L1 data cache latency load logic loop mapping memory microprocessor multiple node on-chip operands optimization order rendering OTIS-hypercube overhead packets parallel partition permutation pipeline pixel power consumption prefetching processing processor profiling proposed ratio reconfigurable reduce redundant operation table reference replica victim cache reuse vector router scheme Section sector server shows simulation simultaneous multithreading speedup structure superscalar switches target threads update value predictor virtual channels wavelength