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THE ATAMM MODEL 4
Figure Page 4 ATAMM model components
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1750A processors ADM system algorithm graph algorithm marked graph algorithm operation AMG node AMG shown ATAMM Multicomputer Operating ATAMM performance plane ATAMM rules available functional units broadcast control edge direct memory access directed circuit dummy node edges and dummy enhanced ATAMM model fault detection fault tolerance firable node firable source global memory grabs the Pi-bus graph data structure graph manager graph node graph play graph status IBM PC/AT injection control input data packet input injection input source instruction set architecture Langley Research Center MICROVAX Multicomputer Operating System multiple concurrent instantiations multiple graphs multiplexing strategy node operation number of resources Old Dominion University operating point output data output sink parallel execution strategy peak resource requirement read transition real-time recursion circuits resource queue shown in Figure single graph sink node source and sink source node system resources TBIO TBIOu TGP diagram throughput performance Triple Modular Redundancy triplicated VHSIC