Alpha Implementations and Architecture: Complete Reference and Guide
Practicing computer engineers and graduate students in computer architecture alike will find this reference book invaluable as it describes the tradeoffs and design philosophy that lead to the development of the Alpha architecture and its implementation. Alpha Architecture and Implementation provides a comprehensive description of all major aspects of Alpha systems. The book includes an overview of the history of RISC development in the computer industry and at Digital, the Alpha Architecture, all the major processor chips, and system implementations. The book also covers RISC concept and design styles, and provides an overview of other RICS architectures and descriptions of the new SPARC, MIPS, Power PC and PA-RISC microprocessors introduced in 1995. The book also discusses operating system porting issues, compiler techniques and binary translation. Dileep Bhankdarkar was a senior consulting engineering in the Alpha Systems Business Group at Digital Equipment Corporation. He has been responsible for leading the technical direction and product strategy of Alpha Personal Systems, Alpha and VAX Servers and High Performance Computing. He was the architecture manager for microVAX, chief architect for VAX vector processing and co-architect of the PRISM RISC architecture on which Alpha is based. He has a BTech degree in electrical engineering from the Indian Institute of Technology in Bombay, and an MS and PhD in electrical engineering from Carnegie-Mellon University. Dileep holds 15 US patents and is senior member of IEEE. He is the author of more than 30 technical publication on computer architecture, semiconductor technology and performance analysis. He currently works for Intel Corporation. Only comprehensive treatise on Alpha Architecture, chips and systems. Insider's view of Alpha A comprehensive discussion of Alpha with overviews of competing architectures.
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RISC Design Issues
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64 bits address bus address space Alpha architecture AlphaServer AlphaStation ASIC Bcache block byte cache misses Cbox chip clock CMOS Compcon Spring compiler Computer contains CRAY T3D cycles data cache Dcache decode Digital dual-issue entry execution external cache fetch floating point floating-point function GJIoating hardware Ibox Icache IEEE implementation instruction cache instruction set integer register interrupt latency load and store load instruction load miss load/store logic longword main memory mapped Mbox microprocessor MIPS mode module multiply on-chip opcode OpenVMS operands operating system PA-RISC page table PALcode performance physical address pipeline pointer port PowerPC PowerPC 620 prefetch processor register provides quadword queue register file result RISC Scache sequence SPARC stage stalls store instruction superscalar system bus Table target tion translation buffer trap TURBOchannel unit virtual address Windows NT Workstation write buffer zero