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4 Pipelined Fulladder I
7 Cell Type I
13 other sections not shown
algorithm Appendix area of metal Black and White BSIM capacitance per unit capacitances of NMOS carry-save adder Chapter chip area clock buffer clock distribution network clock gates clock lines Critical Path Mode critical stage delay drain capacitances exclusive-OR Figure 4.7 Layout gate capacitance GE_nml half-adder horizontal clock skew IGFET Input Signal Layout of Cell Layout of Clock Layout of Second length of gate length ratios logic gate maximum number MOSFETs multiplication scheme NMOS and PMOS number of gates ooo+ao Overlapping Clock Signal parameters partial product phase clock source pipeline stages pipelined multiplier Registers Figure rise and fall Second Stage shown in Figure Signal to Create simulation result smptgl Snm and Pnm source capacitance square unit area square wave stage delay path Time(ns transistors transmission gate Type I Figure Version of Layout vertical clock skew VLSI White Version width of gate width to length WPHI ypop