An Analysis of the Instruction Execution Rate in Certain Computer StructuresThe purpose of the thesis is to present a series of models of digital computers at the level of the memory processor interface. A discussion of computer instructions is presented and the single address format is taken as the prototype instruction. The execution rate for instructions of this type is then determined for several computer structures of the single processor and general multiprocessor types. The effect on the execution rate of a specialized processing activity, input/output handling, is considered. Analytic models relate the instruction execution rate to the memory and processor speeds, their number, and their interconnection. Simulation studies serve to verify the results of the analysis. A simple automatic design program is proposed which optimally configures computer structures from a set of available components. (Author). |
Contents
Computer Components and Instructions | 5 |
Multiprocessor Computers | 35 |
Simulation | 46 |
Copyright | |
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Common terms and phrases
active processor analysis assume average number branch instruction BRARY DIEGO CALIFORN CALIFORNIA UNIVERSITY cessor chapter components compute E(t Computer Configuration computer design computer instruction configurations cost cost/performance ratio design program DIEGO LIBRARY UNIVERSITY digital computers Digital Equipment Corporation fetch fixed point floating point given processor hence i/o activity i/o request instruction execution rate instruction format Instruction Prefetch instruction reference instruction set instructions of class interleaved memory LIBRA LIBRARY SAN DIEGO Magnetic core memories memory and processor memory reference memory request memory restore memory system memory word models multiprocessor number of memories number of occupied number of processors obtained occupied memories operand reference operations performance Poisson process primary memory processor execution processor request processors queued queueing queueing theory random variable SAN DIEGO LIBRARY secondary memories sequence simulation single address format SITY t₁ thesis total memory unit instruction execution UNIV ERSITY usec