An Analysis of the Instruction Execution Rate in Certain Computer Structures
The purpose of the thesis is to present a series of models of digital computers at the level of the memory processor interface. A discussion of computer instructions is presented and the single address format is taken as the prototype instruction. The execution rate for instructions of this type is then determined for several computer structures of the single processor and general multiprocessor types. The effect on the execution rate of a specialized processing activity, input/output handling, is considered. Analytic models relate the instruction execution rate to the memory and processor speeds, their number, and their interconnection. Simulation studies serve to verify the results of the analysis. A simple automatic design program is proposed which optimally configures computer structures from a set of available components. (Author).
What people are saying - Write a review
We haven't found any reviews in the usual places.
Computer Components and Instructions
Single Processor Computers
6 other sections not shown
access memory active processor analysis assume average number branch instruction cessor chapter components Computer Configuration computer design computer instruction computer structures configurations cost cost/performance ratio decode design program determined digital computers Digital Equipment Corporation dynamic priority expected value fixed point floating point given processor hence i/o activity i/o requests instruction execution rate instruction format Instruction Prefetch instruction reference instruction set Instruction Timing Diagram instructions of class instructions per second interleaved memory interval Magnetic core memories memory access memory and processor memory cycle utilization memory locations memory reference memory request memory restore memory system memory word models multiprocessor computer number of memories number of processors obtained occupied memories operand reference operations performance Poisson process primary memory processor execution processor request processors queued queueing queueing theory random variable secondary memories single address format specified by equation thesis tion total memory unit instruction execution usee