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S Cont SCMP Data Bus Demultiplexing the 330
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8048 series microcomputers Address Bus Bidirectional bits BREQ buffer bus access chip clock periods clock signal Control code control signals counter/timer Data Bus Data Counter data memory decrement Delay Direct Memory Access enabled EXT INT external interrupt external logic Halt I/O port illustrated as follows Input High Voltage Input Low Voltage input/output instruction execution instruction fetch instruction set Interface Logic interrupt acknowledge interrupt request interrupt service routine latched Low Voltage vss machine cycle memory addressing memory location microcomputer system microprocessor mode nS CL object code operation Output High Voltage Output Low Voltage PICU Pin Assignments pins and signals Pointer Register ppqq Program Counter program memory Pulse Width read-only memory read/write memory reset ROMC SC/MP SC/MP CPU serial Signals and Pin Status register strobe support devices SYMBOL PARAMETER System Bus timer/counter vDd Volts Voltage vss 0.4 vss 0.4 Volts WRITE