Analysis and Design of Digital Systems with VHDL
ANALYSIS AND DESIGN OF DIGITAL SYSTEMS WITH VHDL integrates industry-standard hardware description language (VHDL) technology into the undergraduate digital logic course. Author Allen Dewey observes that the widespread use of VHDL in specifying digital system designs is driving change and innovation in industry, and defining a new skill set that engineering students must master to design, model, communicate, and implement digital systems. VHDL provides a formal mechanism for describing digital systems in a format easily processed by computers, succinctly capturing the basic concepts of digital systems engineering and harnessing the power of design automation technology. This book first presents combinational and sequential systems and their design, along with logic families and integrated circuits. It then interlocks these subjects with discussions of structural and data flow modeling, synchronous behavior, and algorithmic modeling of digital systems in VHDL. This dual-track organization of conceptual and VHDL-related material makes the book easily adaptable to one- or two-semester courses and a variety of teaching approaches.
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1 4 Design Automation 6 1 5 VHDL 7 1 6 Summary
Decimal 132 3 Binary Arithmetic 172 4 Representing Negative Numbers in Binary 20
21 other sections not shown
4-input A_IN active-1 architecture asserted associated B_IN behavior binary number bit vector Boolean C_IN Chapter clock signal combinational logic combinational system complement component instantiation concurrent signal assignment configuration counter data flow decimal declaration decoder defined denote describe design entity diagram digital system discussed downto edge-triggered encoded end component Equation example flip-flop given in Figure hardware IEEE implementation implicant table input signal input/output INT1 INT2 integrated circuit inverter Karnaugh maps keyword latch literal logic expression logic families logic function logic operators logic schematic Mealy machine memory devices minterms Moore machine MOSFET multiplexer nand gate NMOS notation operands output package prime implicants propagation delay Quine-McCluskey reset sequential system shift register shown in Figure shows signal assignment statement simulation specification STD_ULOGIC structural model sum-of-products switching algebra synchronous tion transistor truth table two's complement type bit user-defined USERJ variables VHDL model voltage