Application-Specific Mesh-based Heterogeneous FPGA Architectures

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Springer Science & Business Media, Nov 5, 2010 - Technology & Engineering - 150 pages
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This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures.
 

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Contents

1 Introduction
1
2 State of the art
9
3 Heterogeneous FPGA Exploration Environment
31
4 FPGA Layout Generation
61
Application Specific Inflexible FPGA
77
6 ASIF using Heterogeneous Logic Blocks
102
7 ASIF Hardware Generation
119
8 Conclusion and Future Lines of Research
138
Bibliography
145
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