Applications of Specification and Design Languages for SoCs: Selected papers from FDL 2005

Front Cover
A. Vachoux
Springer Science & Business Media, Oct 6, 2006 - Technology & Engineering - 312 pages

Applications of Specification and Design Languages for SoCs includes a selection of the best contributions to the Forum on Specification and Design Languages held in 2005 (FDL'05). Since its inception in 1998, FDL has established itself as the premier European forum to exchange experiences and learn about new trends in the application of languages and models for the specification and modeling of electronic systems.

This book provides detailed insights into recent works dealing with a large spectrum of issues in system-on-chip design, namely: assertion-based design, mapping on network-on-chip architectures, use of C/C++/SystemC design methodologies, hardware/software integration, mixing heterogeneous models of computation, analog/mixed-signal/mixed-technology system design and verification, UML/XML-based synthesis of analog and mixed-signal systems, UML to VHDL mapping, UML-based performance modeling, model transformation and formal verification, real-time system models, and Model Driven Architecture.

All chapters in Applications of Specification and Design Languages for SoCs have been carefully revised and extended to offer up-to-date information. They also constitute excellent seeds for further researches and developments in the field of heterogeneous systems-on-chip design.

 

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Contents

4 Experimental Results
165
5 Conclusion
166
References
168
SystemCWMS MixedSignal Simulation Based on Wave Exchanges
170
2 Description and Modeling of Analog Modules in SystemC
173
21 Module Representation with a b Parameters
174
22 Wavechannels
176
3 SystemCWMS Class Library
178

24 Construction of Complex Monitors
13
3 Validation
15
32 Area Comparison
16
4 Implementation of Monitors
17
A Bus Snoop System for Software Verification
19
5 Conclusion
20
Acknowledgments
21
Refining Synchronous Communication onto NetworkonChip BestEffort Services
23
2 Related Work
25
3 Refinement Overview
26
32 Nostrum Communication Services
27
33 The Refinement Procedure
28
4 Channel Refinement
29
5 Process Refinement
30
52 Process Synchronization Property
31
53 Achieving Synchronization Consistency
32
54 Feedback Loops
33
6 Communication Mapping
34
7 Conclusions and Future Work
37
CC++Based System Design
40
Introduction
41
Behaviour Separation A HighLevel Methodology Applicable in the SystemC Environment
43
2 Principles of the Behaviour Separation Methodology
45
3 Application for Communication Protocols
47
4 Realization in SystemC
49
5 Application Example Based on an AMBA AHB Master Device
50
6 IO Adaptation Limitations and Application Fields
54
7 Modelling of Complete AMBA AHB Master Devices and Results
55
8 Extension to Generic Protocols
56
9 Conclusions
58
Mixing Synchronous Reactive and Untimed MoCs in SystemC
61
1 Introduction
62
2 Mapping of SR and Untimed MoCs to SystemC
66
3 UntimedSR MoC Interfaces
73
4 Conclusions
79
References
80
InterfaceCentric Abstraction Level for Rapid HardwareSoftware Integration
82
2 Related Work
85
3 Terminology
86
4 SystemLevel API
87
41 Interface Synthesis
90
42 RTOS Synthesis
93
43 Our HardwareSoftware Codesign Environment
94
5 HardwareSoftware Integration
95
6 Conclusions
97
Efficient and Customizable Integration of Temporal Properties into SystemC
101
2 Property Synthesis
102
21 Intermediate Language
104
31 Property Specification
106
33 Customizing Actions with Policies
108
41 Memory Consumption
109
5 Related Work
110
6 Conclusions and Future Work
111
Acknowledgments
112
UMoC++ A C++Based MultiMoC Modeling Environment
115
1 Introduction
116
2 Related Work
117
31 Preliminary Notations
118
32 Generic MoCs Formulation in SMLSys
119
41 Polymorphic Types
121
42 HigherOrder Functions
122
5 Generic MoCs Formulation in C++
123
51 UMoC++ Framework
124
53 Process Combinators
125
6 Example of Models in our Framework
126
62 Synchronous Data Flow Style Modeling Using UMoC++
127
63 Cosimulation With SystemC
128
References
129
Analog MixedSignal and Heterogeneous System Design
132
Introduction
133
Creating Virtual Prototypes of Complex MEMS Transducers Using ReducedOrder Modelling Methods and VHDLAMS
135
1 Introduction
136
2 Theory of the ReducedOrder Modelling Method
137
3 Micromechanical Yaw Rate Sensor
138
4 Preparation of the FE Models for the ROM Method
140
6 Integration of the ReducedOrder Behavioural Models
143
7 Simulation of the Complete Sensor System
146
8 Conclusions
150
Acknowledgments
151
Modeling Uncertainty in Nonlinear Analog Systems with Affine Arithmetic
155
2 Semisymbolic Simulation with Affine Arithmetic
157
22 Interval Arithmetic versus Affine Arithmetic
158
23 SystemCAMSBased Implementation
159
3 Efficient Handling of Additional Terms in Feedback Control Systems
161
31 Implementation of the Simplification Method
162
32 Comparison of Efficiency
163
4 Application Example
179
41 Simulation Results
183
5 Conclusion
184
Automatic Generation of a Coverification Platform
187
2 Related Work
188
21 Summary
189
3 Design Methodology
190
32 Language Level
191
42 Communication
193
43 Data Type Conversion
194
44 Synchronization
195
5 Automatic Code Generation
196
6 Experimental Example
198
62 Results
200
7 Conclusion
202
UMLXMLBased Approach to Hierarchical AMS Synthesis
204
2 AMS IP Element Requirements for Synthesis Tools
206
3 UML in AMS Design
210
32 Mapping AMS IP Requirements to UML Concepts
211
33 Modelling Analogue Synthesis with Activity Diagrams
213
4 Extensions to Existing Analogue Synthesis Tool runeII
214
41 AMS SoftIP Definition
216
5 Example
218
51 Class Diagram Example
219
52 SoftIP XML File Example
220
Acknowledgments
224
UMLBased System Specification and Design
228
Introduction
229
Compiled and Synthesized UML
231
1 Introduction
232
3 A Theoretical Codesign Approach
233
4 A Practical Codesign Approach
235
5 Translation
236
52 UML Elements
237
53 UML to VHDL Mapping
238
6 Experimentation
242
7 Conclusions
243
72 The 6qx Process
244
References
245
PropertyPreservation Synthesis for Unified Control and DataOriented Models
247
2 Related Research
249
3 RealTime Systems Models
250
4 From a Model to Its Realisation
253
5 Realisation of Systems with TimeIntensive Computations
256
6 Conclusions and Future Work
260
Acknowledgments
261
Traceability and Interoperability at Different Levels of Abstraction in ModelDriven Engineering
263
1 Introduction
264
21 Concepts and Overview of the Metamodel
265
22 More Details on the Metamodel
266
3 Generation of the Trace Model
267
31 Principle of TraceModel Generation
268
32 Example
269
4 Getting Interoperability from Traceability
271
42 Application of the Approach on an Example
273
5 Conclusion
275
Power Simulation of Communication Protocols with StateC
277
2 The StateC Flow
279
3 ImplementationIndependent Model
281
32 Logical Activities Identification and Localization
282
4 ImplementationDependent Model
283
42 Training and Validating the Model
284
5 Power Simulation
285
52 Simulator Usage
288
6 Experimental Results
289
62 Power Characterization of the Models
290
63 Simulator Performance
291
7 Conclusions and Future Work
292
References
293
Integrating ModelChecking with UMLBased SoC Development
295
1 Introduction
296
3 Background
297
31 Overview of CSP and FDR
298
33 UML State Machines
299
4 Translating State Machines to CSP
300
41 Flattening State Machines
301
42 Realizing State Machine Semantics in CSP
302
5 Mapping the Models to CSP
304
53 The Composite Object Model
305
6 The UML2CSP Tool
306
7 Applying FDR to Translated Specifications
307
8 Partial Case Study
308
9 Conclusions
310
References
311
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