Architecture and CAD for deep-submicron FPGAs
Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become one of the most popular implementation media for digital circuits and have grown into a $2 billion per year industry. As process geometries have shrunk into the deep-submicron region, the logic capacity of FPGAs has greatly increased, making FPGAs a viable implementation alternative for larger and larger designs. To make the best use of these new deep-submicron processes, one must re-design one's FPGAs and Computer- Aided Design (CAD) tools. Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPGAs implemented in deep-submicron processes. Three factors combine to determine the performance of an FPGA: the quality of the CAD tools used to map circuits into the FPGA, the quality of the FPGA architecture, and the electrical (i.e. transistor-level) design of the FPGA. Architecture and CAD for Deep-Submicron FPGAs examines all three of these issues in concert. In order to investigate the quality of different FPGA architectures, one needs CAD tools capable of automatically implementing circuits in each FPGA architecture of interest. Once a circuit has been implemented in an FPGA architecture, one next needs accurate area and delay models to evaluate the quality (speed achieved, area required) of the circuit implementation in the FPGA architecture under test. This book therefore has three major foci: the development of a high-quality and highly flexible CAD infrastructure, the creation of accurate area and delay models for FPGAs, and the study of several important FPGA architectural issues. Architecture and CAD for Deep-Submicron FPGAs is an essential reference for researchers, professionals and students interested in FPGAs.
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Background and Previous Work
Packing and Placement
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20 Circuit algorithm annealing schedule area-delay product area-efficiency average benchmark circuits bounding box buffered wires CAD tools channel capacities chapter cluster inputs commercial FPGAs congestion cost function connection block connection-block population cost function critical path delay model depopulated detailed routing architecture disjoint switch block drive strength Elmore delay fanout FPGA architecture FPGA routing global routing architecture I/O pads implemented internal population length 4 buffered length 4 wires logic block array logic block input logic block output logic block pin logic cluster LUTs minimum minimum-width transistor areas multiplexer netlist node number of tracks optimize parameters pass transistor pass-transistor-switched wires perform place and route placement and routing routability routability-driven router routing area routing iteration routing resources routing tracks routing wires routing-resource graph shows simulated annealing sink SRAM switch block topology switch-block population T-VPack tile timing-driven router tracks per channel tri-state buffer VPack wire segments Wmin Xilinx